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Intel details IPU roadmap to free up CPUs

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Intel is betting that future data-center operations will depend on increasingly powerful servers running ASIC-based, programable CPUs, and its wager rides on the development of infrastructure processing units (IPU), which are Intel’s programmable networking devices designed to reduce overhead and free up performance for CPUs.

Intel is among a growing number of vendors—including Nvidia, AWS and AMD—working to build smartNICs and DPUs to support software-defined cloud, compute, networking, storage and security services designed for rapid deployment in edge, colocation, or service-provider networks.

Intel’s initial IPU combines a Xeon CPU and FPGA but ultimately will morph into a powerful ASIC that can be customized and controlled with open system-based Infrastructure Programmer Development Kit (IPDK) software. IPDK runs on Linux and uses programming tools such as SPDK, DPDK and P4 for developers to control network and storage virtualization as well as workload provisioning.

At is inaugural Intel Vision event this week in Texas, Intel talked about other new chips and how AI will play in the data center. It laid out a roadmap for its IPU development and detailed why the device portfolio will be an important part of its data-center plans.

Specific to its IPU roadmap, Intel said it will deliver two 200Gb IPUs by the end of the year. One, code-named Mount Evans, was developed with Alphabet Inc.’s Google Cloud group and at this point will target high-end and hyperscaler data-center servers. 

The ASIC-based Mount Evans IPU can support existing use cases such as vSwitch offload, firewalls, and virtual routing. It implements a hardware-accelerated NVM storage interface scaled up from Intel Optane technology to emulate NVMe devices. 

Copyright © 2022 IDG Communications, Inc.

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